The disclosed technology relates generally to data processing, and more particularly to low-latency programmable encoders.
With the continuing demand for high-reliability transmission of information in digital communication and storage systems, and with the rapid increase in available computational power, various coding and decoding techniques have been investigated and applied to increase the fidelity of these systems. One such coding technique, low-density parity check (LDPC) coding, was first proposed in the 1960s, but was not used until the late 1990s when researchers began to investigate iterative coding and decoding techniques.
LDPC codes are among the few known error control coding techniques capable of transmitting information at a rate close to the Shannon limit or channel-capacity. Currently, LDPC codes are considered to be the next-generation communication system encoding standard. LDPC codes can be regular or irregular, have a linear or cyclic encoding matrix, and can be decoded in a myriad of ways, ranging in complexity and error performance. LDPC codes can also be encoded quite simply because LDPC coding and decoding are generally performed iteratively, reducing the memory requirements for an LDPC encoder. For example, an LDPC encoder is typically implemented using linear or cyclic shift registers, in which the results of the LDPC encoder block matrix-vector multiplication are accumulated in a memory buffer at each calculation step. In particular, the encoding algorithm may be implemented on data processing circuitry, such as a field-programmable gate array (FPGA) or application specific integrated circuit (ASIC). Thus, many LDPC encoders are also programmable, making it easy to change encoding parameters, such as block length or code rate, without having to re-design (or re-build) the LPDC encoders.
However, there are a few concerns with LDPC codes. Lengthy LDPC codes may require large memory buffers and/or computational power, even when the parity-check matrix may be sparse. In addition, the error floor of LDPC codes may be a concern; usually this error floor is high. It may be difficult to implement a low error floor LDPC code without making the code block length large. As mentioned above, if the code block length is large, the LDPC codes may require larger memory buffers. This may be especially true in devices with programmable encoders—e.g., encoders that are operable over a wide range of parameters such as block length, number of block rows, number of block columns, and code rate.
A possible solution for lowering the error floor of an LDPC code may be to use an outer systematic code, such as a Reed-Solomon (RS) or Bose-Chaudhuri-Hocquenghem (BCH) code. However, such codes are typically implemented in a serial manner. For example, a message to be encoded may be first encoded with an outer BCH code, and the resulting code can then be encoded as an LDPC code. Such serially-implemented encoding systems, however, typically require multiple memory buffers and have high latency—e.g., the latency (or time delay in number of codewords) may be as high as 2-3 codewords.